Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Turbo-channel codes conventionally are used to code data. Turbo codes use data in the order in which it is received and in an interleaved order. Original data is therefore used twice. By turbo-channel codes, it is meant convolutional codes. The data is shuffled using an interleaver, and such interleaver may be part of an encoder, a decoder, or an encoder/decoder (“codec”).
Data may be interleaved prior to encoding and then deinterleaved for decoding. In some coding, including either or both encoding and decoding, systems, have high throughputs achieved through parallel processing. Data is generally interleaved by an encoder and deinterleaved by a decoder. Because decoding is more computationally intensive than encoding, and in order to achieve overall system high throughput, deinterleaving should be capable of being implemented in parallel in the decoder.
In the 3rd Generation Partnership Project (“3GPP”), a quadratic permutation polynomial (“QPP”) interleaver is called out in the proposed Long Term Evolution (“LTE”) 3GPP specification to facilitate contention-free addressing. Additional details regarding 3GPP LTE may be found at http://www.3gpp.org. In particular, the 3GPP TS 36.212 version 8.3.0 Technical Specification dated May 2008 discloses channel coding, multiplexing, and interleaving in section 5 thereof, particularly sub-sections 5.1.3, 5.1.4.1.1, and 5.2.2.8 describing a channel interleaver.
Using a QPP interleaver allows individual blocks of data to be split into multiple threads and processed in parallel. If multiple independent blocks of data each have their threads processed, then processing such threads of all such data blocks in parallel involves replicating the QPP interleaver. Accordingly, it should be appreciated that the size and performance of an interleaver circuit used to implement a QPP interleaver affects both efficiency of encoding and decoding turbo-channel codes.